In the production of DRAM (dynamic random access memories) devices, a wafer test and a final test are executed to screen out or sort a fail device which has a defect produced for example in the fabrication process, such as a short circuit between interconnect wires, a non-opening of a contact hole and a short circuit between memory cells. In the wafer test using a wafer prober, a defective cell of the DRAM device is replaced with a redundant memory cell provided in the DRAM device. After the completion of assembly of the DRAM device, the final test is executed using a tester connected with an auto-handler.
In a wafer test or a screening process, a wide variety of accelerated tests need to be executed to guarantee the operation of the device under all environments in the filed and to prevent an initial field incidence ascribable to deterioration of the device and hence an acceleration means for enabling stabilized volume production of the devices is crucial. As the accelerated test of the DRAM devices, for example, an accelerated test of power supply voltage, an accelerated test of operating speed or an accelerated test of tREF (refresh cycle), to say nothing of an accelerated test of operating temperature are executed.
FIG. 4 is a diagram showing the typical configuration of a semiconductor memory device (a DRAM employing a shared sense amplifier). The semiconductor memory device includes a shared sense amplifier 30, used in common by a bit line pair DL1 and /DL1 of a mat1 (MAT1) 11 and a bit line pair DL2 and /DL2 of a mat2 (MAT2) 12, a pair of transfer gates 211 and 212 (path transistors composed by n-channel MOS transistors) for controlling the connection between the bit line pair DL1 and /DL1 of the mat1 (MAT1) and the sense amplifier 30, and a pair of transfer gates 221 and 222 for controlling the connection between the bit line pair DL2 and /DL2 of the mat2 (MAT2) 12 and the sense amplifier 30. The semiconductor memory device also includes sub-word drivers 51 and 52, for driving sub-word lines WL 10 and WL 20, and TG drivers 41 and 42, which receives a MAT1 selection signal and a MAT2 selection signal, respectively, and output signals TG1 and TG2, respectively. The signal TG1 is for performing on/off control of the transfer gates 211 and 212, and the signal TG2 is for performing on/off control of the transfer gates 221, and 222. An output of the sense amplifier 30 is connected via a Y switch, not shown, to an I/O bus line.
The operation of the configuration shown in FIG. 4 will now be described. When the cell connected to the bit line pair DL1 or /DL1 of the MAT1 is to be read, the TG driver 42 set the signal TG2, as its output, to a LOW level, to turn off the transfer gates 221 and 222, for isolating the bit line pair DL2 and /DL2 which is not selected from the sense amplifier 30. The TG driver 41 sets the signal TG1 to a HIGH level to turn on the transfer gates 211 and 212, thereby connecting the a bit line pair DL1 and /DL1 in the MAT1 to the sense amplifier 30. The sub-word driver 51 raises the potential of a selected word line WL10 to a high level. When the selected word line WL10 is raised in its potential, in this manner, the memory cell which is connected to the selected word line, is connected to the bit line DL1. A minor differential voltage (initial differential voltage) is generated between the bit line pair DL1 and /DL1. The sense amplifier 30 amplifies this initial differential voltage to carry out the read operation. At this time, the bit line pair DL2 and /DL2 remains in the precharged state.
As for the shared sense amplifier, reference is to be made to the description of, for example, the Patent Document 1. There is disclosed in Patent Document 2 the connection control of a sense amplifier and a switch.
[Patent Document 1]
JP Patent Kokai Publication No. JP-P2002-109899A
[Patent Document 2]
JP Patent Kokai Publication No. JP-A-07-302497